1. Field of the Invention
The present invention relates to an analog-to-digital converter, especially to a pipelined analog-to-digital converter with low-gain amplifier and calibration of capacitor mismatch and finite gain error of amplifier.
2. Related Art of the Invention
An analog-to-digital converter (ADC) is a device that converts an analog signal into a digital code, i.e. “digitizes” the analog signal. In the field of high speed ADCs, the fastest architecture reported to date is flash converter. However, an ADC based on a flash type will require a huge number of very accurate and fast comparators, which consume large chip area and power. Among various ADC architectures, the pipeline technique is one of the candidates to overcome those drawbacks of the flash-type ADC. Furthermore, the pipeline architecture has been proved that it could provide a better tradeoff among speed, accuracy, power, and chip area than other ADC architectures.
A block diagram of a conventional pipelined ADC with 1.5-bit/stage algorithm is shown in FIG. 1, where the resolution of ADC (100) is, for example, 10 bits. The ADC (100) consists of a sample-and-hold (101), sub-converter stages (102)-(109), a final flash stage (120), and a digital error correction circuit (130). The sample-and-hold (101) samples the input analog signal in sampling phase and then in holding phase generates an analog output which is quantified into a 1.5-bit digital code within the first stage (102). Both the resulting 1.5-bit code of stages (102)-(109) and 2-bit code of final stage (120) are sent to the digital block (130) for processing. The 1.5-bit code of each stage (102)-(109) is fed back to the stage itself to become an analog representation. The difference between the analog representation and the sampled analog input signal is multiplied by two to produce a residue signal which is sampled by the next stage. Each stage effectively converts only one bit of information and the extra half bit is used for redundancy to relieve the offset requirement of comparators. Digital error correction circuit (130) deals with the redundancy to generate a 10-bit digital result (each of the sub-converter stages (102)-(109) contributes 1 bit and the flash stage (120) contributes 2 bits). In the conventional pipelined ADC, the sample-and-hold (101) may be removed, and the resolution of flash stage (120) may be more than 2 bits, such as 3, 4, 5, 6, 7, 8, 9 bits.
The circuit diagrams of sub-converter stages (102)-(109) are identical, as illustrated in FIG. 2A (sampling phase) and FIG. 2B (holding phase). The examples in FIG. 2A (sampling phase) and FIG. 2B (holding phase) are single-ended but may be differential in practice and the same below. One sub-converter stage (200) comprises an amplifier (201), two capacitors C1 and C2, two comparators (210) and (211), and a digital unit (220). During sampling phase, as shown in FIG. 2A, the output and inverting input of amplifier (201) are connected together with the top plates of both C1 and C2. The non-inverting input of amplifier (201) is connected to a dc voltage (it's ground in the figure). The input analog signal Vin is sampled parallel on the bottom plates of C1 and C2, and further fed to comparators (210) and (211) to compare with two reference voltages (Vref/4 and −Vref/4) respectively. The digital unit (220) receives the results of the two comparators and provides a digital output Di (−1, 0, or 1). During holding phase, as shown in FIG. 2B, the amplifier (201) is in amplification mode and its inverting input is still connected with the top plates of both C1 and C2. The bottom plate of C2 is connected with the output of amplifier (201). Depending on the value of Di, the bottom plate of C1 is connected with different reference voltages (−Vref, 0, or Vref). As a result, the output of amplifier (201) is decided by the input analog signal Vin, Di, capacitance ratio of C1 and C2, the gain A of amplifier (201), and reference voltage Vref. In order to achieve an ideal multiplication of two of the input analog signal Vin for the output Vout, C1 and C2 should be perfectly matched and the gain of amplifier (201) should be infinite.
FIG. 3 is a graph illustrating the ideal transfer characteristics of a 1.5-bit/stage conventional sub-converter stage. When Vin equals to Vref/4 and −Vref/4, it corresponds to two thresholds or transition points.
In the above-mentioned pipelined architecture, the performance of ADC suffers from both the mismatch of capacitor and the finite amplifier gain. Many calibration approaches have been proposed to compensate the capacitor mismatch, such as U.S. Pat. No. 6,184,809 and U.S. Pat. No. 7,233,276. The finite amplifier gain error can be also calibrated, such as U.S. Pat. No. 6,784,814 and U.S. Pat. No. 6,563,445. Moreover, digital calibration procedure U.S. Pat. No. 6,232,898 corrects both the capacitor mismatch and finite amplifier gain. But these methods are generally difficult to implement, time consuming and/or with additional conversion process steps.